| 000 | 01390nam a22003137a 4500 | ||
|---|---|---|---|
| 001 | ENG-90614 | ||
| 005 | 20060929121129.0 | ||
| 008 | 080729t xxu||||| |||| 00| 0 eng d | ||
| 010 | _aENG-90614 | ||
| 020 |
_a0070252211 _c395.00 |
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| 035 | _aEN-74147 | ||
| 037 | _bDBAD / PUB | ||
| 040 | _aDPL | ||
| 082 | _a621.392 | ||
| 100 | _aNavabi, Zainalabedin. | ||
| 245 |
_aVerilog digital system design : _bRT level synthesis, testbench, and verification / _cby Zainalabedin Navabi. |
||
| 250 | _a2nd ed. | ||
| 260 |
_aNew Delhi _bTata McGraw-Hill Publishing _c2008. |
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| 300 |
_axvi, 384 p. : _bill. _c24 cm. (pbk) _e1 CD-ROM (4 3/4 in.) |
||
| 500 | _aIncludes bibliographical references and index. | ||
| 650 | _aVerilog (Computer hardware description language) | ||
| 650 |
_aElectronic digital computers _xComputer-aided design. |
||
| 856 | _uhttp://www.loc.gov/catdir/enhancements/fy0668/2006271457-b.html | ||
| 856 | _uhttp://www.loc.gov/catdir/enhancements/fy0668/2006271457-d.html | ||
| 856 | _uhttp://www.loc.gov/catdir/enhancements/fy0668/2006271457-t.html | ||
| 942 |
_2ddc _cEN _h621.392 _mNAV |
||
| 999 |
_c14630 _d14630 |
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